This application claims the priority of Korean patent application Serial No. 2001-51826 filed on Aug. 27, 2001.
1. Field of the Invention
The present invention relates to a mask ROM and a fabrication method thereof, and in particular to a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof.
2. Description of the Background Art
A mask ROM is a non-volatile device for discriminating data and recording necessary information according to a mask process in an element isolation process, a metal process or an ion implant process for a channel region of a memory cell.
FIG. 1 is a layout diagram illustrating a memory cell of a conventional flat cell type mask ROM.
The flat cell type mask ROM has been widely used in a fabrication method using a logic process.
Referring to FIG. 1, the flat cell type mask ROM includes: a substrate 100 where a memory cell array region I and a segment select region II are defined; a trench (not shown) formed at the outer portion of the memory cell array region I of the substrate 100; an element isolating film (not shown) filling up the trench; a plurality of buried layers 110 aligned on the resultant structure in a first direction by a predetermined interval; and a plurality of gates 114 aligned in a second direction to cross the buried layers 110 in an orthogonal direction.
In the fabrication process of the flat cell type mask ROM, an isolation process is performed at the outer portion of the memory cell array region I to surround the whole memory cell array region I, instead of performing a LOCOS or STI process for isolating memory cells. A source/drain junction of the memory cell is the buried layer 110 formed before the gate process. It is thus unnecessary to isolate the junctions.
A contact 122 of the buried layer junction does not exist in the memory cell array region I but in the segment select region II. In addition, a width of the gate 114 is a channel width of the memory cell.
As described above, the isolating film and the contact are not formed in the memory cell, and thus a size of the memory cell is about 4F2 (xe2x80x98Fxe2x80x99 implies a minimum line width of photolithography), thereby improving integration, simplifying the whole process and cutting down production costs.
When a logic process of a design rule below 0.35 xcexcm is applied to the fabrication process of the flat cell type mask ROM, 1) the isolation process is performed by LOCOS, 2) N type impurity-doped polysilicon, Ti-Salicide or W-Polycide is used as the gate formation material, and 3) Ti-Salicide identical to the gate formation material is employed as the source/drain junction.
In addition, when the flat cell type mask ROM is fabricated according to a logic process of a design rule below 0.25 xcexcm, 1) the isolation process is performed to surround the whole memory cell array region by a trench STI, 2) Ti-Salicide or Co-Salicide is used as the gate formation material, and 3) Ti-Salicide or Co-Salicide identical to the gate formation material is employed as the source/drain junction.
Accordingly, the flat cell type mask ROM having compatibility with the logic process of a design rule below 0.35 xcexcm has been commercially used. There are therefore increasing demands for a flat cell process having compatibility with the logic process below 0.25 xcexcm.
FIG. 2 is a flowchart showing a conventional flat cell type mask ROM process.
As illustrated in FIG. 2, the conventional method for fabricating the mask ROM includes: an isolation process for forming an element isolating film at the outer portion of a memory cell array region; a well formation process; a buried layer formation process; a process for forming a gate insulating film and gates in the memory cell array region and its peripheral region; a cell isolation ion implant process for implanting ions to the memory cell array region; a process for forming a source/drain in the gates of the peripheral region; a coding process; a process for forming a contact in a buried layer of a segment select region; and a bit line formation process.
FIGS. 3a through 3c are cross-sectional diagrams, taken along lines AB, BC and CD of FIG. 1. In FIGS. 3a to 3c, xe2x80x98axe2x80x99 denotes an active region of the memory cell array region, and xe2x80x98bxe2x80x99 denotes a peripheral region which is the outer portion of the active region.
The conventional method for fabricating the mask ROM will now be described in detail with reference to FIGS. 3a to 3c. 
As depicted in FIG. 3a, provided is a substrate 100 where a memory cell array region I and a segment select region II are defined.
A trench 103 is formed by etching the outer portion of the active region (a) of the memory cell array region I of the substrate 100. Thereafter, an insulating film such as an oxide silicon film is deposited over the resultant structure, and etched according to an etch back process or a chemical mechanical polishing process, to form an element isolating film 104 filling up the trench 103.
A well 102 is formed on the substrate 100 having the element isolating film 104 according to an impurity implant process. Here, the element isolating film formation process may be performed after the well formation process, as depicted in FIG. 3B.
Thereafter, a photolithography process and an impurity implant process are sequentially carried out in the memory cell array region I and the segment select region II of the substrate 100 having the well 102, thereby forming buried layers 110, 111 aligned in one direction.
A gate insulating layer 112 is positioned on the substrate 100, to form gates 114 aligned in an orthogonal direction to the buried layers 110, 111.
Although not illustrated, a cell isolation ion implant process is performed in the active region (a) of the memory cell array region I, a source/drain 130 is formed in the peripheral region (b), and a coding process is performed thereon.
As shown in FIG. 3c, a protective film 120 is deposited on the substrate 100, and a contact 122 serving as a passage to a bit line (not shown) to be formed according to a succeeding process is formed on the buried layer 111 of the segment select region II.
Then, the bit line electrically connected to the buried layer 111 of the segment select region II through the contact 122 is formed, and thus fabrication of the mask ROM is finished.
When the mask ROM is fabricated according to the logic process of a design rule below 0.25 xcexcm, the element isolating film is formed according to the shallow trench isolation and the chemical mechanical polishing process.
In general, one segment of the memory cell consists of 32 word lines and 1024 bit lines. When a size of the segment is decreased, an area of the memory cell having the same integration is increased. Considering that the gate is designed under the minimum design rule, a height of the 32 word lines is approximately 64F. When it is presumed that a height of the segment select end is about 12F, a height of the segment is 76F, and a length of the 1024 bit lines is about 2048F. That is, a size of the segment is represented by xe2x80x982048Fxc3x9776Fxe2x80x99. In the case of the design rule below 0.25 xcexcm, the size of the segment is represented by xe2x80x98512Fxc3x9719 xcexcmxe2x80x99.
The memory cell is an aggregate of the segments. For example, 128 segments are required to compose a 4M bit memory cell array. Therefore, a size of the 4M bit memory cell is approximately xe2x80x98512Fxc3x972432 xcexcmxe2x80x99, which is a size of the active region composing a memory cell block.
However, in the conventional method for fabricating the mask ROM, a polishing speed is not uniform in the wide active region of the memory cell array region. As a result, polishing uniformity is reduced in a memory cell larger than xe2x80x98200 xcexcmxc3x97200 xcexcmxe2x80x99.
In addition, the buried layer is patterned in a minimum size allowable in the photolithography. It is thus difficult to pattern the buried layer in the boundary portion between the segment select region and the memory cell array region.
Accordingly, it is an object of the present invention to provide a method for fabricating a mask ROM which can improve polishing uniformity in a polishing process in the element isolating film formation, and which can easily pattern a buried layer in a boundary portion between a segment select region and a memory cell array region.
In order to achieve the above-described object of the present invention, there is provided a mask ROM including: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.
There is also provided a method for fabricating a mask ROM including the steps of: providing a substrate where a memory cell array region and a segment select region are defined; forming an element isolating film and an isolating pattern at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; forming a plurality of buried layers aligned over the resultant structure in a first direction by a predetermined interval, and surrounded by the isolating pattern; and forming a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.